(1) Field of the Invention
The present invention relates to a computer bus, and more particularly, to a method and apparatus for performing distributed address decode, transferring variable length data bursts and selectively locking resources coupled to the bus.
(2) Art Background
Computer data buses are used throughout the computer industry to transfer data between data processing resources ("agents") coupled to the bus. Personal Computers (PCs) were originally designed with a single bus structure to which all the resources of the computer were coupled. As PCs matured, some vendors added an additional bus for the CPU to communicate to memory at a higher speed. In the prior art, the addition of a memory bus required a centralized decoder to tell the memory when the transaction was addressed to the memory and to tell the standard bus when it should intercept the cycle. A distributed address decoding environment is more flexible, because it allows any number of devices to be coupled to the bus, without necessitating the configuration of a centralized resource which has a mapping of the memory and input/output (I/O) space addresses of each device.
Many large (non-PC) computer buses require read or write operations to be directed to an address of an agent which is coupled to the bus. If a read or write occurs to a non-existent address, these buses require that an error state occur and that corrective action be taken. However, it is common for PC software to perform dummy read or write transactions to non-existant addresses. Toward that end, distributed address decode creates a problem in determining that no device on the bus has been addressed, so that the access can be routed to the standard PC bus as required by the PC software paradigm.
As will be described, the present invention provides a method and address for performing distributed address decode on a bus thereby avoiding the requirement that there be a centralized decoder which has a mapping of the memory and I/O space addresses of each device coupled to the bus.
Furthermore, many computer buses in use today allow bursts of data to be transmitted to one or more agents. In most cases, the data burst must be of a specific length. A few buses do allow a master agent to notify the slave agent as to how many data words will make up the burst, and allow the slave to indicate that it cannot take or supply additional data. Although some point-to-point data links support streaming data types of potentially infinite length, few shared computer buses in use today allow for such a transfer. In most shared computer buses that permit data bursts, if the length of the data burst is not a standard size (i.e. a block transfer), the master and slave must negotiate the length of the burst before the transfer can occur. Then, if the transfer is interrupted, a catastrophic error will occur and the entire data burst must be repeated or the transfer aborted.
As will be described, the present invention allows an infinite length transfer to progress as long as the bus arbiter continues to permit the master agent to retain control of the bus. In the preferred embodiment, one data word moves across the bus on every cycle that the master and slave can transmit and receive the data (allowing either agent to slow down the transfer if needed).
Most operations between agents on the bus are atomic operations (e.g., single read or write operations). Some operations are non-atomic operations because they involved more than one transaction. For example, in a read-modify-write operation, a master agent will read data from a slave agent, modify the data which was read, and then write the modified data back to the slave agent in the location from which the data was read. There will be an interval when the bus is unused while the master is modifying the data before writing it back. Data corruption can occur, if, during the interval that the first master is modifying the data, another master agent uses the bus to read or write data to the location on the slave where data will be written at the conclusion of the read-modify-write operation.
Many computer buses incorporate a lock semantic to allow a device to complete a non-atomic operation as if it were atomic. In most cases, a total bus lock is implemented. However, a total bus lock reduces the bus bandwidth available for other masters on the bus by not allowing any other accesses to occur while the lock is held.
Other implementations have an address based lock that increases the bandwidth available to other master agents on the bus by permitting the other masters to access addresses of non-locked agents during the intervals of non-atomic operations when the bus is free. In the address based lock schemes, central memory logic stores the locked addresses and issues back-down signals to any masters (except the locking master) that attempt to access locked addresses. In this way, other masters can access non-locked addresses while a master has locked the addresses of one or more slave agents. While the address lock scheme increases the bandwidth of the bus, the central memory logic increases the complexity and cost of the bus interface.